{"id":48,"date":"2024-06-25T11:17:03","date_gmt":"2024-06-25T11:17:03","guid":{"rendered":"https:\/\/study.madeeasy.in\/?p=48"},"modified":"2025-09-08T15:42:59","modified_gmt":"2025-09-08T10:12:59","slug":"what-do-you-mean-by-machine-instructions","status":"publish","type":"post","link":"https:\/\/www.madeeasy.in\/study\/cs-it\/what-do-you-mean-by-machine-instructions","title":{"rendered":"What do you mean by Machine Instructions?"},"content":{"rendered":"\r\n<p style=\"text-align: justify;\">A set of binary codes that are recognised and executed directly by a processor is called a machine code. An individual machine code is called a machine instruction.<\/p>\r\n<p style=\"text-align: justify;\">Main memory holds <a href=\"https:\/\/study.madeeasy.in\/cs-it\/what-do-you-mean-by-machine-instructions\/\" target=\"_blank\" rel=\"noopener\">machine instructions<\/a> and data.<\/p>\r\n<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_79_1 ez-toc-wrap-left counter-hierarchy ez-toc-counter ez-toc-light-blue ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><a href=\"#\" class=\"ez-toc-pull-right ez-toc-btn ez-toc-btn-xs ez-toc-btn-default ez-toc-toggle\" aria-label=\"Toggle Table of Content\"><span class=\"ez-toc-js-icon-con\"><span class=\"\"><span class=\"eztoc-hide\" style=\"display:none;\">Toggle<\/span><span class=\"ez-toc-icon-toggle-span\"><svg style=\"fill: #999;color:#999\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" class=\"list-377408\" width=\"20px\" height=\"20px\" viewBox=\"0 0 24 24\" fill=\"none\"><path d=\"M6 6H4v2h2V6zm14 0H8v2h12V6zM4 11h2v2H4v-2zm16 0H8v2h12v-2zM4 16h2v2H4v-2zm16 0H8v2h12v-2z\" fill=\"currentColor\"><\/path><\/svg><svg style=\"fill: #999;color:#999\" class=\"arrow-unsorted-368013\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"10px\" height=\"10px\" viewBox=\"0 0 24 24\" version=\"1.2\" baseProfile=\"tiny\"><path d=\"M18.2 9.3l-6.2-6.3-6.2 6.3c-.2.2-.3.4-.3.7s.1.5.3.7c.2.2.4.3.7.3h11c.3 0 .5-.1.7-.3.2-.2.3-.5.3-.7s-.1-.5-.3-.7zM5.8 14.7l6.2 6.3 6.2-6.3c.2-.2.3-.5.3-.7s-.1-.5-.3-.7c-.2-.2-.4-.3-.7-.3h-11c-.3 0-.5.1-.7.3-.2.2-.3.5-.3.7s.1.5.3.7z\"\/><\/svg><\/span><\/span><\/span><\/a><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/www.madeeasy.in\/study\/cs-it\/what-do-you-mean-by-machine-instructions\/#Fields-of-an-Instruction\" >Fields of an Instruction:<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/www.madeeasy.in\/study\/cs-it\/what-do-you-mean-by-machine-instructions\/#Instruction-Cycle\" >Instruction Cycle<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/www.madeeasy.in\/study\/cs-it\/what-do-you-mean-by-machine-instructions\/#Fetch-Cycle\" >Fetch Cycle<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/www.madeeasy.in\/study\/cs-it\/what-do-you-mean-by-machine-instructions\/#Execution-Cycle\" >Execution Cycle<\/a><\/li><\/ul><\/nav><\/div>\n<h3 style=\"text-align: justify;\"><span class=\"ez-toc-section\" id=\"Fields-of-an-Instruction\"><\/span>Fields of an Instruction:<span class=\"ez-toc-section-end\"><\/span><\/h3>\r\n<ul style=\"text-align: justify;\">\r\n<li><strong> Opcode:<\/strong> The operation itself is usually represented by a code called the opcode.<\/li>\r\n<li><strong>Address:<\/strong> Other than opcode, all the other parts of an instruction are called address or operand fields.<\/li>\r\n<li><strong>Mode:<\/strong> It specifies the way the operand or effective address is determined. It may be implicit or explicit in the instruction.<\/li>\r\n<\/ul>\r\n<p style=\"text-align: justify;\"><img loading=\"lazy\" decoding=\"async\" class=\"size-full wp-image-41 aligncenter\" src=\"http:\/\/study.madeeasy.in\/wp-content\/uploads\/2024\/06\/me-machine-instruction.jpg\" alt=\"Machine Instruction \" width=\"349\" height=\"71\" \/><\/p>\r\n<h3 style=\"text-align: justify;\"><span class=\"ez-toc-section\" id=\"Instruction-Cycle\"><\/span>Instruction Cycle<span class=\"ez-toc-section-end\"><\/span><\/h3>\r\n<p style=\"text-align: justify;\">Instruction cycle describes the execution sequence of the program instruction contain two sub cycles:<\/p>\r\n<ul style=\"text-align: justify;\">\r\n<li>Fetch cycle<\/li>\r\n<li>Execution cycle<\/li>\r\n<\/ul>\r\n<p style=\"text-align: justify;\"><img loading=\"lazy\" decoding=\"async\" class=\"size-full wp-image-42 aligncenter\" src=\"http:\/\/study.madeeasy.in\/wp-content\/uploads\/2024\/06\/instruction-cycle.png\" alt=\"Instruction Cycle\" width=\"197\" height=\"242\" \/><\/p>\r\n<h3 style=\"text-align: justify;\"><span class=\"ez-toc-section\" id=\"Fetch-Cycle\"><\/span>Fetch Cycle<span class=\"ez-toc-section-end\"><\/span><\/h3>\r\n<ul style=\"text-align: justify;\">\r\n<li>Objective of a fetch cycle is instruction fetch. In this process, CPU fetch the instruction from main memory based on program counter.<\/li>\r\n<\/ul>\r\n<h3 style=\"text-align: justify;\"><span class=\"ez-toc-section\" id=\"Execution-Cycle\"><\/span>Execution Cycle<span class=\"ez-toc-section-end\"><\/span><\/h3>\r\n<ul style=\"text-align: justify;\">\r\n<li>Objective of a execution cycle is processing of an instruction.<\/li>\r\n<li>CPU organisation is classified in the three types based on the availability of \u201cALU operands\u201d:\r\n<ol style=\"list-style-type: lower-roman;\">\r\n<li>Stack CPU<\/li>\r\n<li>Accumulator CPU<\/li>\r\n<li>General register CPU<\/li>\r\n<\/ol>\r\n<\/li>\r\n<\/ul>\r\n<p style=\"text-align: justify;\"><strong># Stack CPU<\/strong><\/p>\r\n<ul style=\"text-align: justify;\">\r\n<li>In this organization ALU operations are performed only on stack data means both of the operands are always required into stack.<\/li>\r\n<\/ul>\r\n<p style=\"text-align: justify;\"><strong># Accumulator CPU<\/strong><\/p>\r\n<ul style=\"text-align: justify;\">\r\n<li>In this organisation, for ALU operation Ist operand is always required in the accumulator while 2nd operand may be present either in the register or in the memory.<\/li>\r\n<\/ul>\r\n<p style=\"text-align: justify;\"><strong># General register CPU<\/strong><\/p>\r\n<ul style=\"text-align: justify;\">\r\n<li>Based on the number of registers possible in the <a href=\"https:\/\/study.madeeasy.in\/cs-it\/operating-system\/what-is-cpu-scheduling-and-its-types\/\" target=\"_blank\" rel=\"noopener\">CPU<\/a>, architecture is divided into two categories: <br \/># Register to memory reference CPU. <br \/># Register to register reference CPU.<\/li>\r\n<\/ul>\r\n<p style=\"text-align: justify;\"><strong>#Register to memory reference CPU:<\/strong><\/p>\r\n<ol style=\"text-align: justify;\">\r\n<li style=\"list-style-type: none;\">\r\n<ol>\r\n<li>In this architecture, number of registers are less in comparison with register to register reference CPU.<\/li>\r\n<li>In this architecture, for performing ALU operation it is needed to store first operand in the register while second operand can either be in register\/memory.<\/li>\r\n<li>After processing, result is stored in the source 1 register.<\/li>\r\n<li>Compatible instruction format: \u201c2 address instruction\u201d<\/li>\r\n<\/ol>\r\n<\/li>\r\n<\/ol>\r\n<p style=\"text-align: justify;\"><img loading=\"lazy\" decoding=\"async\" class=\"size-full wp-image-43 aligncenter\" src=\"http:\/\/study.madeeasy.in\/wp-content\/uploads\/2024\/06\/execution-cycle.png\" alt=\"Execution Cycle\" width=\"319\" height=\"63\" \/><\/p>\r\n\r\n\r\n\r\n<p style=\"text-align: center;\"><a class=\"btn btn-danger\" role=\"button\" href=\"https:\/\/study.madeeasy.in\/cs-it\/computer-organization-and-architecture\/what-do-you-mean-by-flynns-classification\/\" target=\"_blank\" rel=\"noopener\">&lt;&lt; Previous<\/a> | <a class=\"btn btn-success\" role=\"button\" href=\"https:\/\/study.madeeasy.in\/cs-it\/what-do-you-mean-by-addressing-modes-and-its-types\/\" target=\"_blank\" rel=\"noopener\"> Next &gt;&gt;<\/a> <br \/><strong> Must Read: <\/strong> <a href=\"https:\/\/study.madeeasy.in\/subjects\/what-is-computer-organization-and-architecture\/\" target=\"_blank\" rel=\"noopener\"><strong>What is Computer Organization and Architecture?<\/strong><\/a><\/p>\r\n<p style=\"text-align: justify;\">\u00a0<\/p>\r\n","protected":false},"excerpt":{"rendered":"<p>A set of binary codes that are recognised and executed directly by a processor is called a machine code. An<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[3,4],"tags":[21,22,23,24],"class_list":["post-48","post","type-post","status-publish","format-standard","hentry","category-cs-it","category-computer-organization-and-architecture","tag-execution-cycle","tag-fetch-cycle","tag-instruction-cycle","tag-machine-instructions"],"_links":{"self":[{"href":"https:\/\/www.madeeasy.in\/study\/wp-json\/wp\/v2\/posts\/48","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.madeeasy.in\/study\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.madeeasy.in\/study\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.madeeasy.in\/study\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.madeeasy.in\/study\/wp-json\/wp\/v2\/comments?post=48"}],"version-history":[{"count":0,"href":"https:\/\/www.madeeasy.in\/study\/wp-json\/wp\/v2\/posts\/48\/revisions"}],"wp:attachment":[{"href":"https:\/\/www.madeeasy.in\/study\/wp-json\/wp\/v2\/media?parent=48"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.madeeasy.in\/study\/wp-json\/wp\/v2\/categories?post=48"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.madeeasy.in\/study\/wp-json\/wp\/v2\/tags?post=48"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}